Register Definition:
Status Register : B7 - B0
  Bit        Name                               Settings:
  5-2        Block Protection Bits [3:0]        See protected area table

Configuration Register: B7 - B0
  Bit        Name                               Settings:
   3         TB (Top/Bottom Select)             0: Top protected (Default), 1: Bottom protected (OTP)

Configuration Register 2 at address 0x40000000: B7 - B0
  Bit        Name                               Settings:
   3         CRCEN# (Enable Parity Checking)    0: Enable (OTP), 1: Disable (Default)
   1         DEFDOPI#                           0: Enable (OTP), 1: Disable (Default)
   0         DEFSOPI#                           0: Enable (OTP), 1: Disable (Default)

    DEFDOPI# and DEFSOPI# control the default peripheral interface mode of the device on power up.
    When both are set to '1' then the default mode is SPI. When DEFDOPI# is set to '0' and DEFSOPI# 
    is set to '1' then the default mode is DTR OPI. When DEFDOPI# is set to '1' and DEFSPOI# is set 
    to '0' then the default mode is STR OPI. Both set to '0' is an invalid value and is blocked.

Security Register: B7 - B0
  Bit        Name                               Settings:
   7         WPSEL (Write Protection Select)    0: Block Protection Mode (Default), 1: Advanced Sector Protection Mode (OTP)
   1         LDSO (Lock-Down Secured OTP)       0: Not Lock-Down (Default), 1: Lock-Down (OTP)

Fast Boot Register: B31 - B0
  Bit        Name                               Settings:
 31-4        FBSA (FastBoot Start Address)      Boundary address for start of boot code access
  2-1        FBSD (FastBoot Start Delay Cycle)  See FastBoot Delay table
   0         FBE (FastBoot Enable)              0: FastBoot Enable, 1: FastBoot Not Enable (Default)

    Give the necessary data in the format of FF-FF-FF-FF. Where each byte of data to be written to the Fast Boot Register is
    separated by the - character.

Lock Register: B7 - B0
  Bit        Name                               Settings:
   6         SPBLKDN (SPB Lock Down)            0: Not Enabled (Default), 1: Enabled (OTP) (Becomes volatile and default if PPML is enabled)
   2         Password Protection Mode Lock      0: PPML Enable (OTP), 1: Solid Protection Mode (Default)

Password Register: B63 - B0
  Bit        Name                               Settings:
 63-0        PWD (Hidden Password)              64 byte password (OTP)

    The Password Register can not be changed in any way once it has been written to once. Give the necessary data in the format
    of FF-FF-FF-FF-FF-FF-FF-FF. Where each byte of data to be written to the Fast Boot Register is separated by the - character.

WPSEL:
    When WPSEL is Enabled, the Block Protection bits (Status register bits 5-2) no longer performs any function and become read only.
    The Block Protection bits (Status register bits 5-2) will be permanently set to a value of 1.
    The TB (Top/Bottom select) no longer performs any function.

Sector Protection Mode:
    A SPB register is assigned to each 4KB sector in the top and bottom 64KB of memory and to each 64KB block in the remaining memory.
    Settings the SPB register of a sector/block to 0xFF will protect the data in that sector/block from modification.
    This device has 542 SPB registers, indexed 0 - 541
    To set a single SPB register, enter its index
    Example: To set SPB at index 13, enter 13

    To set a range of SPB registers, separate the low and high register indexes with a hyphen
    Example: To set SPBs at indexes 3 - 17, enter 3-17

    To specify multiple indexes or ranges, separate the indexes or ranges with a comma
    Example: To set SPB at indexes 13, 22 - 27, 31 - 40, and 47, enter 13,22-27,31-40,47

Additional Notes:
    4K Customer OTP Area:
        - May be locked by the customer (Lock-Down secured OTP bit in the security register)
    4K Factory OTP Area:
        - May only be locked by the factory
        - May contain unique identifiers placed by the factory