Device Register description:

Status Register:
  Bit        Name                                               Settings:    
   7         SRWD                                               0: Enabled (Default), 1: Disabled
   5         TB                                                 0: Top (Default), 1: Bottom
  6,4-2      BP[3:0]                                            See Protected Area table, 0: (Default)   

Configuration Register (Address: 0x0Bh):
  Bit        Name                                               Settings: 
   7         Reserved                                           1: (Default)
   6         SSOENB                                             0: DQ3 Inverted, 1: DQs are same (Default)
  5-4        CRCSIZE                                            00: 128-byte, 01: 64-byte, 10: 32-byte, 11: 16-byte (Default)
   3         WCRCENB                                            0: CRC Enabled, 1: CRC Disabled (Default)
   2         ERRBECC                                            0: ERR# LOW indicates 1-bit correction, 1: ERR# indicates 2-bit detection (Default)
   1         ERRBENB                                            0: ERR# ON, 1: ERR# OFF (Default)
   0         ECCENB                                             0: ECC ON, 1: ECC OFF (Default)

Configuration Register (Address: 0x0Ah):
  Bit        Name                                               Settings:    
  7-0        DLP Pattern                                        55h: Bit 7 is MSB (Default)

Configuration Register (Address: 0x07h):
  Bit        Name                                               Settings:    
  7-0        Wrap Configuration                                 FFh: Continuous (Default), FEh: 64-byte wrap, FDh: 32-byte wrap, FCh: 16-byte wrap

Configuration Register (Address: 0x06h):
  Bit        Name                                               Settings:    
  7-0        XIP Configuration                                  FFh: XIP Disabled (Default), FEh: 8IOFR XIP, FDh: 8OFR XIP, F8h: Fast Read XIP

Configuration Register (Address: 0x05h):
  Bit        Name                                               Settings:    
  7-0        Address Configuration                              FFh: 3-byte Address (Default), FEh: 4-byte Address

Configuration Register (Address: 0x03h):
  Bit        Name                                               Settings:    
  7-0        Drive Output Strength                              FFh: 50 ohm (Default), FEh: 75 ohm, FDh: 35 ohm, FCh: 18 ohm

Configuration Register (Address: 0x01h):
  Bit        Name                                               Settings:    
  5-0        Dummy Cycle Configuration                          1Fh: (Default), 1Eh: 30 dummy cycles, 03h-1Dh: 3-29 dummy cycles
                                                                02h: 2 dummy cycles, 01h: 1 dummy cycle, 00h: Identical to 1Fh

Configuration Register (Address: 0x00h):
  Bit        Name                                               Settings:    
  7-0        I/O Mode                                           FFh: Extended SPI (Default), DFh: Extended SPI without DQS, E7h: Octal DDR, C7h: Octal DDR without DQS

Lock Bit Security Register:
  Bit        Name                                               Settings:    
  7-0        Protection Status                                  00h: Sector PROTECTED from modify operations, FFh: Sector UNPROTECTED from modify operations (Default)

Password:
  Bit        Name                                               Settings:    
  63-0       Password                                           64-bit Password (OTP)

Sector Protection Register:
  Bit        Name                                               Settings:    
  15-3       Reserved                                           1: (Default)
   2         Password Protection Lock                           1: Disabled (Default), 0: Enabled (OTP)
   1         Sector Protection Lock                             1: Enabled with Password Protection (Default), 0: Enabled without Password Protection (OTP)
   0         Reserved                                           1: (Default)

Protection Management Register:
  Bit        Name                                               Settings:    
  7-5        Reserved                                           1: (Default)
   4         Status Register Lock                               1: Unlock (Default), 0: Lock (OTP)
   3         Reserved                                           1: (Default)
   2         PMR Lockdown                                       1: Unlock (Default), 0: Lock (OTP)
   1         Sector lock bit register lockdown                  1: Unlock (Default), 0: Lock (OTP)
   0         Sector lock bit erase lock                         1: Unlock (Default), 0: Lock (OTP)

OTP Array Control Byte (Byte 64):
  Bit        Name                                               Settings:    
  7-1        Reserved                                           1: (Default)
   0         OTP Control Bit                                    1: Unlock (Default), 0: Lock (OTP)

Additional Notes:
    Lock Bit Security Register default to 0xFF
    Setting a sector to 0x00 will protect the data in that sector from modification.

    This device has 256 sectors, indexed 0 - 255

    To set a Lock Bit Security Register, enter its index
    Example: To set Sector at index 13, enter 13

    To set a range, separate the low and high register indexes with a hyphen
    Example: To set Sectors at indexes 3 - 17, enter 3-17

    To specify multiple indexes or ranges, separate the indexes or ranges with a comma
    Example: To set Sectors at indexes 13, 22-27, 31-40 and 47, enter 13,22-27,31-40,47

All registers are assumed to be nonvolatile.
