Device Register description:
Status Register 1:
  Bit        Name                                           Settings:    
   7         Status Register Protect 0                      0: Disabled (Default), 1: Enabled
   6         Sector/Block Protect                           0: Disabled (Default), 1: Enabled
   5         Top or Bottom Protection                       0: Top (Default), 1: Bottom
  4-2        BP[2:0]                                        000: Default, See Protected Area table

Configuration Register 1:
  Bit        Name                                           Settings:    
   6         Complement Protection                          0: Disabled (Default), 1: Enabled
  5-2        Security Region Lock Bits [3:0]                0: Unlocked (Default), 1: Locked (OTP)
   1         QUAD                                           0: Disabled (Default), 1: Enabled
   0         Status Register Protect 1                      0: Disabled (Default), 1: Enabled (OTP)

Configuration Register 2:
  Bit        Name                                           Settings:    
   7         IO3_Reset                                      0: Disabled (Default), 1: Enabled
  6-5        Output Impedance                               11: Default, See Output Impedance Control table
   3         QPI                                            0: Disabled (Default), 1: Enabled
   2         Write Protect Selection                        0: Legacy Protection (Default), 1: Individual Block Lock
   1         Address Length at Power-Up                     0: 3-Byte Address (Default), 1: 4-Byte Address

Configuration Register 3:
  Bit        Name                                           Settings:    
  6-5        Wrap Length                                    11: 64 Byte Wrap (Default), 10: 32 Byte Wrap, 01: 16 Byte Wrap, 00: 8 Byte Wrap
   4         Weap Enable                                    1: Disabled (Default), 0: Enabled
  3-0        Read Latency                                   1000: Default, 0 to 15 latency (dummy) cycles following read address or continuous mode bits

Data Learning Register:
  Bit        Name                                           Settings:    
  7-0        Data Learning Pattern                          0: Default, 1: Value for DDR Read Command Latency (OTP)

Individual and Region Protection Register:
  Bit        Name                                           Settings:    
   6         Security Region 3 Read Password Mode Enable    1: Disabled (Default), 0: Enabled (OTP)
   4         IBL Lock Boot                                  1: Disabled (Default), 0: Enabled (OTP)
   2         Password Protection Mode Lock                  1: Disabled (Default), 0: Enabled (OTP)
   1         Power Supply Lock-down Protection Mode Lock    1: Disabled (Default), 0: Enabled (OTP)
   0         Permanent Protection Lock                      1: Disabled (Default), 0: Enabled (OTP)

Password Register:
  Bit        Name                                           Settings:
 63-0        Password                                       64 byte password (OTP)

Pointer Region Protection Register:
  Bit        Name                                           Settings:
 23-12       PRP Address                                    1: Pointer Address (Default), See PRP Table for details
  11         PRP Protect All                                1: Protect All Sectors (Default), 0: Protect Pointer Region Selected Sectors
  10         PRP Enable                                     1: Disable Pointer Region Protection (Default), 0: Enable Pointer Region Protection
   9         PRP Top/Bottom                                 1: Bottom (Default), 0: Top

Additional Notes:

    Status Register Protect 1 Bit:
        This bit in Configuration Register 1 is only programmable prior or at the same time as IRP[2:0] is '111', otherwise it will reloaded to '0'. 
        At default state, Status Register and all 3 Configuration Registers are not protected.
        When this bit is enabled, these registers are permanently locked.

    IRP Register:

        Security Regions Read Password Mode:                Protects Security Region 3 from read, program and erase
        IBL Lock Boot:                                      Sets All IBL Bits to be in UNPROTECTED state following power-up, hardware reset, or software reset
        Password Protection Mode:                           Protects Security Regions 2 and 3 and Pointer Region, Unprotected WITH password
        Power Supply Lock-down Protection Mode:             All IRP Bits are locked and protected from further programming
        Permanent Protection Mode:                          Protects Security Regions 2 and 3 and Pointer Region
    
    General IRP Register Guidelines
    
    Password Protection Mode, Power Supply Lock-down Protection Mode, and Permanent Protection Mode are mutually exclusive - only one option can be programmed
    Security Regions Read Password Mode if desired, must be programmed prior or at the same time as Password Protection Mode
        This mode is not active until password is programmed and Password Protection Mode is enabled
        Security Region 3 is not readable when this mode is enabled
    IBL Lock Boot if desired, must be programmed prior or at the same time as setting one of Protection Modes (IRP[2:0])

    Once a Protection Mode is selected, any attempt to change any bits in IRP Register will fail.


    Pointer Region Protection Register:

        This register can be used in combination with either Legacy Block Protection or Individual Block Lock Protection methods. When enabled, it is logically ORed with
        the protection method selected by WPS bit

        The pointer boundary set by the PRP Address is the block boundary between the protected and the unprotected regions in memory.
        The area that is unprotected will be inclusive of the 4KB sector selected by the pointer value.
        PRP Top/Bottom determines whether the region that is unprotected will start from the top or bottom of the memory array to the location of the pointer.