Device Register description:
Status Register:
  Bit        Name                                       Settings:    
   7         Status Register Write Disable              0: Not Write-Protected (Default), 1: Write-Protected
   6         QE - Quad Bit                              0: Disabled (Default), 1: Enabled
  5-2        BP[3:0]                                    See Protected Area table

Function Register
  Bit        Name                                       Settings:    
   7         IRL3 - Lock the Info Row                   0: IRow3 can be programmed (Default), 1: IR can not be programmed (OTP)
   6         IRL2 - Lock the Info Row                   0: IRow2 can be programmed (Default), 1: IR can not be programmed (OTP)
   5         IRL1 - Lock the Info Row                   0: IRow1 can be programmed (Default), 1: IR can not be programmed (OTP)
   4         IRL0 - Lock the Info Row                   0: IRow0 can be programmed (Default), 1: IR can not be programmed (OTP)
   1         Top/Bottom Selection (TBS)                 0: Top (Default), 1: Bottom (OTP)
   0         Dedicated RESET# Disable Bit               0: Dedicated RESET# enabled (Default), 1: Dedicated RESET# disabled (OTP)

Read Register
  Bit        Name                                       Settings:    
   7         HOLD#/Reset#                               0: HOLD# pin is selected, 1: RESET# pin is selected
  6-3        Dummy Cycles                               Number of Dummy cycles
   2         Burst Length Enable                        0: Disabled (Default), 1: Enabled
  1-0        Burst Length                               00: 8Bytes (Default), 01: 16Bytes, 10: 32Bytes, 11: 64Bytes

Extended Read Register
  Bit        Name                                       Settings:    
  7-5        Output Drive Strength                      111: 50% (Default)
   4         Reserved - will read as 1 

AutoBoot Register
  Bit        Name                                       Settings:
 31-5        AutoBoot Start Address
  4-1        AutoBoot Start Delay
   0         AutoBoot Enable                            0: Disabled (Default), 1: Enabled

Bank Address Register
  Bit        Name                                       Settings:    
   7         3-Byte or 4-Byte Addressing                0: 3-Byte (Default), 1: 4-Byte

Advanced Sector/Block Protection Register
  Bit        Name                                       Settings:    
  15         Top Bottom Selection                       0: High Address (OTP), 1: Low Address (Default)
 14-3        Reserved - will read as 1
   2         Password Protection Mode Lock              0: Enabled (OTP), 1: Disabled (Default)
   1         Persistent Protection Mode Lock            0: Enabled (OTP), 1: Disabled (Default)
   0         Reserved - will read as 1

Password Register
  Bit        Name                                       Settings:    
  63-0       PSWD - 64 bit hidden password              64-bit Password (OTP)

PPB Register Register
  Bit        Name                                       Settings:    
  7-0        Protect Read or Program per sector         00 = Protects sector addressed by RDPPB/PGPPB command from program or erase operations
                                                        FF = Not protecting addressed by RDPPB/PGPPB command sector from program or erase operations (Default)

Software Write Protection:
    The device provides two kinds of software write protection, Block Protection bits (BP3, BP2, BP1, BP0)
    and Advanced Sector/Block Protection (ASP). When Block Protection is enabled (i.e., any BP3-0 are set to ?1?),
    Advanced Sector/Block Protection (ASP) can still be used to protect sectors/blocks not protected by the Block Protection scheme.
    
    Warning: ASP and Block Protection should not be used concurrently. Use one or the other, but not both.
    In the case that both ASP and Block Protection are used on the same sector/block the logical OR of ASP and Block Protection is used.

Advanced Sector Protection:
    There can only be one protection mode lock chosen. An attempt to program in both modes results in programming failure and the operation will abort.

    In the devices default state a Persistent Protection bit register is assigned to each 4KB sector in the BOTTOM 128KB's of memory
    and to each 64KB block in the remaining memory. However if the TBPARM bit is set to 0 then a Persistent Protection bit register is assigned
    to each 4KB sector in the TOP 128KB's of memory and to each 64KB block in the remaining memory

    PPB registers default to 0xFF
    Setting the PPB register of a sector/block to 0x00 will protect the data in that sector/block from modification.
    This device has 286 PPB registers, indexed 0 - 285

    To set a single PPB register, enter its index
    Example: To set PPB at index 13, enter 13

    To set a range of PPB registers, separate the low and high register indexes with a hyphen
    Example: To set PPB at indexes 3 - 17, enter 3-17

    To specify multiple indexes or ranges, separate the indexes or ranges with a comma
    Example: To set PPB at indexes 13, 22-27, 31-40 and 47, enter 13,22-27,31-40,47