Device Register description:
Status Register 1:
  Bit        Name                               Settings:    
   7         Status Reg Write Disable (SRWD)    0: No Protection(Default), 1: Locks state of SRWD, BP, and Configuration Register-1 bits
  4-2        BP[2:0]                            See Protected Area table

Status Register 2:
  Bit        Name                               Settings:    
   7         Block Erase Size                   0: 64KB Erase (Hybrid) (Default), 1: 256KB Erase (Uniform) (OTP)
   6         Page Buffer Wrap                   0: Wrap at 256B (Default), 1: Wrap at 512B (OTP)
   5         IO3 Reset                          0: HOLD# (Default), 1: RESET# (OTP)

Configuration Register 1:
  Bit        Name                               Settings:    
  7-6        LC[1:0] Latency Code               (Default 00) See Latency Code Tables
   5         BP Start (TBPROT)                  0: BP starts at top (Default), 1: BP starts at bottom (OTP)
   3         BP Non-Volatile (BPNV)             0: BP is Non-Volatile (Default), 1: BP is Volatile (OTP)
   2         Pram sector Location (TBPRAM)      0: 4Kb sectors at bottom (Default), 1: 4Kb sectors at top (OTP)
   1         Quad I/O Mode                      0: Disabled (Default), 1: Enabled

AutoBoot Register
  Bit        Name                               Settings:    
 31-9        AutoBoot Start Address
  8-1        AutoBoot Start Delay
   0         AutoBoot Enable                    0: Disabled(default), 1: Enabled

Advanced Sector Protection Register:
  Bit        Name                               Settings:
   2         Password Protection Mode           0: Enabled (OTP), 1: Disabled (Default)
   1         Persistent Protection Mode         0: Enabled (OTP), 1: Disabled (Default)

Password Register:
  Bit        Name                               Settings:    
 63-0        64 bit hidden password             64-bit Password (OTP)

1024-byte OTP Address Space (Secure Silicon Region):
    The OTP address space is divided into 32, individually lockable, 32-byte regions, indexed (31-0).
    Regions 31-1 are blank when shipped from the factory and function as 32-byte, lockable OTP areas.
    Region 0 however contains a 128 bit random number and the lock bits for regions (31-0).
    The lowest 16 bytes in region 0 (address 0xF - 0x0) contain a 128 bit random number programmed by Cypress.
    The next 4 bytes in region 0 (address 0x13 - 0x10) are the Lock bits for OTP regions 31-0.
    The remaining 12 bytes in region 0 (address 0x1F - 0x14) are (Reserved for future use).
    Only the 4 Lock bytes in region 0 (address 0x13 - 0x10) can be programmed, any other data provided for region 0 will be ignored.

    Data will start being programmed/verified at Region 1 (0x20).

TBPROT,TBPARM & Block Erase Size:
    The desired state of the TBPROT,TBPARM & Block Erase Size bits must be selected during the initial configuration of the device,
    before the first program or erase operation on the main flash array. 
    The TBPROT,TBPARM & Block Erase Size bits must not be programmed after programming or erasing is done in the main flash array. 
    TBPARM (CR[2]) becomes RFU when Uniform Sector Mode is selected (SR2[7] = 1) and attempts to change its value will fail

Advanced Sector Protection:
    Once the Advanced sector protection register has been programmed in anyway (a protection mode has been selected) the following
    OTP bits are permanently locked and attempts programming the OTP bits will fail.

    SR2[7:5] - Status Register 2 OTP bits 7 - 5
    ASPR - Advanced Sector Protection Register
    PASS - Password Register

    In the devices default state a Persistent Protection bit register is assigned to each 64KB block in memory with the exception of the BOTTOM
    64KB's which is divided into 16 4KB sectors.
    
    If the TBPARM bit is set to 0 then a Persistent Protection bit register is assigned to each 64KB block in memory with the exception of the TOP
    64KB which is divided into 16 4KB sectors.

    The parameter sector can also be removed by setting the Block Erase Size to Uniform 256KB Sectors (SR2[7] = 1).

    PPB registers default to 0xFF
    Setting the PPB register of a sector/block to 0x00 will protect the data in that sector/block from modification.

    With 64KB sectors the device has 271 PPB registers, indexed 0 - 270

    With 256KB sectors the device has 64 PPB registers, indexed 0 - 63

    To set a single PPB register, enter its index
    Example: To set PPB at index 13, enter 13

    To set a range of PPB registers, separate the low and high register indexes with a hyphen
    Example: To set PPB at indexes 3 - 17, enter 3-17

    To specify multiple indexes or ranges, separate the indexes or ranges with a comma
    Example: To set PPB at indexes 13, 22-27, 31-40 and 47, enter 13,22-27,31-40,47