Register definition:
Status Register 1 - STR1N:
  Bit      Name                                     Settings:    
  4-2      LBROT[2:0]                               See Protected Area table

Configuration Register 1 - CFR1N:
  Bit      Name                                     Settings:
   6       SP4KBS: Split 4kB selection              0: 4k sectors grouped together,   1: 4k sectors split between high and low address (Default)
   5       TBPROT: Top or Bottom Protection         0: Top half address range (Default),        1: Bottom half address range
   4       PLPROT: Permanent Locking                0: Status/Config 1 Unprotected (Default),   1: Status/Config 1 Protected (OTP)
   2       TB4KBS: Top or Bottom Address Range      0: 4kb sector at bottom address (Default),  1: 4kb sector at top address range
   
Configuration Register 2 - CFR2N:
  Bit      Name                                     Settings:    
   7       ADRBYT: Address Byte Length              0: 3-Byte Addressing (Default),             1: 4-Byte Addressing 
  3-0      MEMLAT[3:0]: Memory Read Latency         1000: 8 dummy cycles (Default), See Latency code (cycles) table

Configuration Register 3 - CFR3N:
  Bit      Name                                     Settings:    
  7-6      VRGLAT[1:0]: Volatile Read Latency       00: 0/0/32 Latency cycles (Default), See Register Latency code (cycles) table
   5       BLKCHK: Blank Check Selection            0: Disabled during erase (Default),         1: Enabled
   4       PGMBUF: Program buffer size              0: 256 Bytes (Default),                     1: 512 Bytes
   3       UNHYSA: Uniform or Hybrid Sectors        0: Hybrid Sector Architecture (Default),    1: Uniform Sector Architecture

Configuration Register 4 - CFR4N:
  Bit      Name                                     Settings:    
  7-5      IOIMPD[2:0]: I/O Driver Output           000: 45 Ohms, 001: 120, 010: 90, 011: 60, 100: 45, 101: 30 (Default), 110: 20, 111: 15
   4       RBSTWP: Read Burst Wrap                  0: Disabled (Default),                      1: Enabled
   3       ECC12S: ECC selection                    0: 1-bit Detection/Correction (Default),    1: 1-bit Detection/Correction & 2-bit Error Detection
   2       DPDPOR: Deep Power Down                  0: Standby Mode (Default),                  1: Deep Power Down Power Mode
  1-0      RBSTWL[1:0]: Read Burst Wrap Length      00: 8-Bytes (Default), 01: 16-Bytes, 10: 32-Bytes, 11: 64-Bytes

Configuration Register 5 - CFR5N:
  Bit      Name                                     Settings:    
   6       Reserved                                 1: Default
   1       SDRDDR: Octal SDR/DDR Selection          0: SDR enabled (Default),                   1: DDR enabled
   0       OPI-IT: Octal Interface Selection        0: Single SPI (1S-1S-1S) (Default),         1: Octal Protocol (8S-8S-8S, 8D-8D-8D)

Advanced Sector Protection Register - ASPO:
  Bit      Name                                     Settings:    
   5       ASPRDP: Read Password Protection Select  1: Disabled (Default),                      0: Enabled (OTP)
   4       ASPDYB: DYB Protection at Power-Up       1: Disabled (Default),                      0: Enabled (OTP)
   3       ASPPPB: PPB for Sectors Program Select   1: PPB Erase is Enabled (Default)           0: PPB Erase is Disabled (OTP)
   2       ASPPWD: Password Protection Select       1: Disabled (Default),                      0: Enabled (OTP)
   1       ASPPER: Persistent Protection Select     1: Disabled (Default),                      0: Enabled (OTP)
   0       ASPPRM: Permanent Protection Select      1: Disabled (Default),                      0: Enabled (OTP)

Password Register - PWDO:
  Bit      Name                                     Settings:   
  64-0     PWDO[63:0]: Password                     64-bit Password (OTP)

ASP PPB Access Register - PPAV:
  Bit      Name                                     Settings:   
  7-0      PPBACS[7:0]: Sector Based PPB Protect    FF: Unprotected Sector (Default)            00: Protected Sector

AutoBoot Register - ATBN:
  Bit      Name                                     Settings:  
  32-9     STADR[22:0]: Start Addr to Read          000h: Default                               XXXh: Address Bits
  8-1      STDLY[7:0]: Read Start Delay             00h: Default                                XXh: Address Bits
   0       ATBTEN: AutoBoot Feature Selection       0: Disabled (Default)                       1: Enabled

Endurance Flex Architecture Selection Register - EFXx - Pointers 1-4:
  Bit      Name                                     Settings:  
  10-2     EPTADx[8:0]: Pointer Addr Select         1FFh: Default                               XXXh: Address of beginning sector (OTP)
   1       ERGNTx: Pointer based Region Type        1: High Endurance Sectors (Default)         0: Long Retention Sectors (OTP)
   0       EPTEBx: Pointer Enable# Select           1: Disabled (Default)                       0: Enabled (OTP)

Endurance Flex Architecture Selection Register - EFXx - Pointer 0:
  Bit      Name                                     Settings:  
   1       GBLSEL: All Sectors Based Region Type    1: High Endurance Sectors (Default)         0: Long Retention Sectors (OTP)
   0       WRLVEN: Wear Leveling Enable Select      1: Enabled (Default)                        0: Disabled (OTP)

Secure Silicon Region Locking Bits:
  Bit      Name                                     Settings:  
  7-0      Region Locking Bits (0x10)               1: Unprotected                              0: Permanent Protected Secure Region (OTP)
 15-8      Region Locking Bits (0x11)               1: Unprotected                              0: Permanent Protected Secure Region (OTP)
 23-16     Region Locking Bits (0x12)               1: Unprotected                              0: Permanent Protected Secure Region (OTP)
 31-24     Region Locking Bits (0x13)               1: Unprotected                              0: Permanent Protected Secure Region (OTP)


Additional Notes:

    Secure Silicon Region (OTP)

    Strongly Recommended to offset data file in Secure Silicon Region by 0x20 and only program from 0x20-0x3FF (992 bytes)
    First 16 Bytes (Region 0) has manufactured programmed random number, next 4 bytes are User Configurable for region locking bits, 
        remaining 12 bytes in region are reserved. 0x40h to 0x3FFh are available for user programming

    Region Locking Bits: 1 bit per secure region (32 bits in total) to permanently protect once set to 0. Bit 0 in Region Locking Bits (0x10) corresponds to Region 0,
        Bit 7 in Region Locking Bits (0x13) corresponds to Region 31.



    Security Protection
        Read + Password Protection              Protects Read/Program/Erase to Memory Array, ASP Register, PPB Bits, Status & Configuration Register,
                                                    but Unprotected Read Sector based on TBPROT
        Password Protection:                    Protects Program/Erase to Memory Array, ASP Register, PPB Bits
        Persistent Protection:                  Protects ASP Register, PPB Bits, Password Register, Configuration Register 1, Configuration Register 3 (Bit 3)
        Permanent Protection:                   Protects ASP Register, PPB Bits
        PPB for all Sectors Programmability:    Disables Erasing PPB Bits
        DYB for all Sectors at Power-Up:        Locks DYB at Power-Up

    
    General ASP Guidelines
    
    Persistent protection (ASPPER) and password protection (ASPPWD) are mutually exclusive - only one option can be programmed
    Read password protection (ASPRDP) if desired, must be programmed at the same time as password protection (ASPPWD)
    Once the password is programmed and verified, the password protection scheme (ASPPWD) must be programmed (to 0) to prevent reading the password
    When device is in ASPPWD, Unable to read Password, thus unable to verify Password.
    Programming memory spaces or writing registers is not allowed when Read Password Protection Mode is active.

    
    
    ASP PPB Access Register

    PPB Bits will default to 0xFF. Setting a sector to 0x00 will protect the data in that sector from modification.
    This device has 128 sectors, indexed 0 - 127
    If the device is set up to not have uniform sectors, it has 160 sectors, indexed 0 - 159

    To set a PPB, enter its index
    Example: To set Sector at index 13, enter 13

    To set a range, separate the low and high register indexes with a hyphen
    Example: To set Sectors at indexes 3 - 17, enter 3-17

    To specify multiple indexes or ranges, separate the indexes or ranges with a comma
    Example: To set Sectors at indexes 13, 22-27, 31-40 and 47, enter 13,22-27,31-40,47