Register definition:
Status Register : B7 - B0
  Bit        Name                              Settings:
   7         Status Register Write Protect     0: Disabled(Default), 1: Enabled
   6         Quad Enable                       0: Disabled, 1: Enabled
  5-2        Block Protection Bits[3:0]        See Protected Area table

Configuration Register : B7 - B0
  Bit        Name                              Settings:
   3         TB (top/bottom select)(OTP)       0: Top protect(default), 1: Bottom protect (OTP)

Fast Boot Register : B31 - B0
  Bit        Name                              Settings:
 31-4        FastBoot Start Address            Boundary address for start of boot code access
  2-1        FastBoot Start Delay              See FastBoot Delay table
   0         FastBoot Enable                   0: FastBoot Enable 1: FastBoot Not Enable(Default)

Security Register : B7 - B0
  Bit        Name                              Settings:
   7         Write Protection Select           0: Block(Default) 1: Sector (OTP)
   1         Lock-down Secured OTP             0: Unlocked 1: Locked (OTP)

Lock Register : B15 - B0
  Bit        Name                              Settings:
   2         Password Protection Mode Lock     1: PPM Not Enable(Default) 0: PPM Enable (OTP)
   1         Solid Protection Mode Lock        1: SPM Not Enable(Default) 0: SPM Enable (OTP)

Password Register : B63 - B0
  Bit        Name                              Settings:
 63-0        Hidden Password                   64 byte Password (OTP)

WPSEL:
    When WPSEL is Enabled, the Block Protection Mode bits (SRWD and bp[3-0]) no longer preform any function and become read only.
    The Block Protection Bits[3-0] (bits 5-2 of the Status Register) will be permanently set to a value of 1.
    The Status Register Write Protect Bit (bit 7 of the Status Register) will be permanently set to it's current value.

Sector Protection Mode:
    An SPB register is assigned to each 4KB sector in the bottom and top 64KB of memory and to each 64KB block in the remaining memory.
    Setting the SPB register of a sector/block to 0xFF will protect the data in that sector/block from modification.
    This device has 542 SPB registers, indexed 0 - 541

    To set a single SPB register, enter its index
    Example: To set SPB at index 13, enter 13

    To set a range of SPB registers, separate the low and high register indexes with a hyphen
    Example: To set SPBs at indexes 3 - 17, enter 3-17

    To specify multiple indexes or ranges, separate the indexes or ranges with a comma
    Example: To set SPB at indexes 13, 22-27, 31-40 and 47, enter 13,22-27,31-40,47

Additional Notes: 
    1. The first 128 bits of the OTP Area may have been programmed with a unique identification number by the factory.
    If the device has been programmed with a unique identification number, programming of the first 128 bits of the OTP area must be avoided