Register definition:
Status Register 1: B7 - B0
  Bit        Name                              Settings:
   7         Status Register Write Protect     0: Disabled(Default), 1: Enabled
   6         Quad Enable                       0: Disabled, 1: Enabled
  5-2        Block Protection Bits[3:0]        See Protected Area table

Configuration Register: B7 - B0
  Bit        Name                              Settings:
   3         TB (top/bottom select)(OTP)       0: Top protect(default), 1: Bottom protect (OTP)

Security Register: B7 - B0
  Bit        Name                              Settings:
   7         Write Protection Select           0: Block(Default) 1: Individual Block Protection(OTP) 
   1         Lock-down Secured OTP             0: Unlocked 1: Locked (OTP)

This Version does support Factory Mode - Enhanced performance on programming and erase.

WPSEL:
    When WPSEL is Enabled, the Block Protection Mode bits (SRWD and bp[3-0]) no longer preform any function and become read only.
    The Block Protection Bits[3-0] (bits 5-2 of the Status Register) will be permanently set to a value of 1.
    The Status Register Write Protect Bit (bit 7 of the Status Register) will be permanently set to it's current value.

Additional Notes: 
    The first 128 bits of the OTP Area may have been programmed with a unique identification number by the factory.
    If the device has been programmed with a unique identification number, programming of the first 128 bits of the OTP area must be avoided